Defining virtualized page attributes based on guest page attributes

ABSTRACT

A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.

RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.15/260,893, filed Sep. 9, 2016, which is herein incorporated byreference in its entirety.

TECHNICAL FIELD

The present disclosure relates to memory management and, morespecifically, to specify certain attributes of memory frames based onattributes of guest physical address (GPA) pages.

BACKGROUND

A computing device may include one or more processing cores in one ormore processors (such as central processing units (CPUs)) for executinginstructions and a memory device (such as random-access memory (RAM))for storing instructions and data associated with executing tasks(including user application and system application such as the kernel ofan operating system) on the one or more processing cores. Instructionsof each application program may access the memory using virtualaddresses (or linear addresses) in a virtual memory address space. Amemory management unit may use a page table to translate virtualaddresses into physical addresses of the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure will be understood more fully from the detaileddescription given below and from the accompanying drawings of variousembodiments of the disclosure. The drawings, however, should not betaken to limit the disclosure to the specific embodiments, but are forexplanation and understanding only.

FIG. 1 illustrates a processing system to protect the memory accordingan embodiment of the present disclosure.

FIG. 2 illustrates a flowchart to show the process of memory addresstranslation according to an embodiment of the present disclosure.

FIG. 3 illustrates an extended page table according to an embodiment ofthe present disclosure.

FIG. 4 is a block diagram of a method to perform memory address mappingaccording to an embodiment of the present disclosure.

FIG. 5A is a block diagram illustrating a micro-architecture for aprocessor including heterogeneous core in which one embodiment of thedisclosure may be used.

FIG. 5B is a block diagram illustrating an in-order pipeline and aregister renaming stage, out-of-order issue/execution pipelineimplemented according to at least one embodiment of the disclosure.

FIG. 6 illustrates a block diagram of the micro-architecture for aprocessor that includes logic in accordance with one embodiment of thedisclosure.

FIG. 7 is a block diagram illustrating a system in which an embodimentof the disclosure may be used.

FIG. 8 is a block diagram of a system in which an embodiment of thedisclosure may operate.

FIG. 9 is a block diagram of a system in which an embodiment of thedisclosure may operate.

FIG. 10 is a block diagram of a System-on-a-Chip (SoC) in accordancewith an embodiment of the present disclosure

FIG. 11 is a block diagram of an embodiment of an SoC design inaccordance with the present disclosure.

FIG. 12 illustrates a block diagram of one embodiment of a computersystem.

DETAILED DESCRIPTION

Certain hardware processor architectures provide mechanism to supportmemory address mappings (e.g., from guest physical address space to hostphysical address space). For example, a processor may execute a virtualmachine monitor (VMM) that may support multiple virtual machines (VMs).Each VM may include a guest operating system and run guest softwareapplications. The VMM may employ an auxiliary page table (referred to asthe extended page table (EPT)) to translate guest physical addresses(GPAs) used by a guest operating system to the host physical addresses(referred to as physical addresses) for accessing the memory used by theprocessor of the host machine. The guest physical address space may beorganized as pages (referred to as guest memory pages) of a fixed size(e.g., 4 KB) identified by identifiers (referred to as GPA page numbers)associated with the guest memory pages. The host physical address spacemay be organized as memory frames of a fixed size (e.g., 4 KB)identified by identifiers (referred to as memory frame numbers)associated with memory frames.

In some implementations, the VMM may specify certain access rights tothe memory frames, where the access rights define the limitations for aguest software application to access these memory frames. The accessrights may include rights for read (R), write (W), and/or execute (X).Each right may be specified using a flag (e.g., one-bit flag) stored ina register so that if it is enabled (e.g., flag=“1”), the guest softwareapplication has the corresponding type of access rights; if it isdisabled (e.g., flag=“0”), the guest software application does not havethe corresponding type of access rights.

The EPT may include multiple entries referred to as EPT entries (EPTEs)that each stores a memory mapping from one or more guest memory pages inthe GPA space to one or more memory frames in the physical addressspace, and a plurality of access right flags associated with thesememory frames. The VMM specifies the access rights based on the guestphysical address and certain attributes of the guest physical address(e.g., user mode or supervisor mode). VMM, however, does not rely uponon the access rights for a corresponding virtual address which arespecified by the guest OS. The guest operating system may have specifiedthe access rights of these guest memory pages to constrain access tothese guest memory pages by guest software applications under the guestoperating system controls.

In general, the VMM may seek to use memory address mapping tables suchas the extended page table (EPT) to protect memory without needing toknow the details of how guest software intends to manage the memory. Inmany situations, however, the VMM may need to enhance the memoryprotection further with certain attributes of the virtual addressassigned by the guest operating system of the virtual machine. Forexample, the VMM may want to specify protections to a memory frame basedon a page mode (e.g., supervisor mode or user mode) for a virtualaddress specified by the guest operating system. The page mode is a bit(U/S bit) assigned to a virtual address page by the guest operatingsystem to control the access to the page. If the bit is set (e.g., to“1”) to the user mode, it can be accessed by both applications runningin the user mode and the supervisor mode. If the bit is set (e.g., to“0”) to the supervisor mode, it can be accessed only by applicationsrunning in the supervisor mode. If the underlying hardware architecturedoes not provide for the EPTEs to account for the page mode, the VMMneeds to apply the most restrictive permissions among different pagemodes to the frame, ensuring that the processor does not allow anyundesired accesses. This approach may require the VMM to intercept everymemory access request made by the virtual machine to the memory frame.The examination of the page modes associated with the page by the VMMmay degrade VMM performance.

Embodiments of the present disclosure include an expanded set of accessright flags that the VMM may specify how access rights may be based onone or more paging attributes controlled by the guest OS (e.g., theuser/supervisor mode). The VMM may specify the access rights accordingto rules stored in a policy data structure. For example, the existingaccess right flags stored in an EPTE may be expanded from (R, W, X) to(RU, WU, XU, RS, WS, XS), wherein (RU, WU, XU) are the access rights of“read”, “write”, and “execute” associated with the user mode assigned toa virtual address by the guest operating system, and (RS, WS, XS) arethe access rights of “read”, “write”, and “execute” associated with thesupervisor mode assigned to a virtual address by the guest operatingsystem. The VMM may specify these access rights according to the pagemode specified by the guest OS.

FIG. 1 illustrates a processing system 100 to protect the memoryaccording an embodiment of the present disclosure. Processing system 100may include a host computer 150 that may further include a processor(such as a central processing unit (CPU)) 102 and a memory 104 that iscommunicatively coupled to processor 102. In one embodiment, processor102 and memory 104 may be fabricated on a system-on-a chip (SoC). Thememory 104 may store system application and user application programs,and the data associated with these programs. The processor 102 mayexecute tasks such as system applications and user applications usingthe memory 104 to store the instructions of the programs and dataassociated with the programs.

The processor 102 may further include one or more processing cores 106,a memory management unit (MMU) 108, one or more control registers 112.Processing cores 106 are logic circuits within the processor 102 forexecuting certain tasks (e.g., software applications). In oneembodiment, the tasks executed on processing cores 106 do not access thememory 104 directly using the physical addresses of the memory. Instead,the tasks access a virtual memory through virtual addresses (also knownas linear addresses). The memory management unit 108, coupled betweenthe processing cores 106 and the memory 104, may map the virtualaddresses of the virtual memory to the physical addresses of the memory104. The space of virtual addresses may be divided into fixed sizedunits called pages. A page of the virtual addresses may be mappedcorrespondingly into a fixed-sized unit in the physical address space ofthe memory 104 called a memory frame.

In one embodiment, processor 102 may include a logic circuit implementedto support execution of a set of virtualization instructions (e.g.,virtual-machine extension (VMX)) to provide support for one or morevirtualization environments ported on host 150. The VMX may provideprocessor-level support for virtual machines. In one embodiment, the VMXmay include instructions to support a virtual machine monitor (VMM) 114that is a host program that allows one or more execution environments(or virtual machines (VMs)) to run on the host 102. Referring to FIG. 1,VMM 114 may create and run virtual machines (VMs) 116.

VMs 116 may behave like a hardware computing device to end users. Forexample, VMs 116 may each include a virtual processor (not shown) thatemulates a hardware processor. The virtual processor associated with VMs116 may support a respective guest operating system (guest OS) 118.Guest applications 120 may run within the environments of guestoperating systems 118. Guest operating systems 118 (including kernels)can include a number of guest-OS components (or kernel components) toprovide a number of services to guest applications 120. In oneembodiment, these guest-OS components run at the same processorprivilege level (e.g., the highest ring 0 privilege level). In oneembodiment, the guest-OS provided services may include scheduler,process management, I/O management, memory management, drivers (e.g.,file system and volume drivers, mass storage drivers, and bus drivers),and code integrity management services. The ring 0-2 privilege levelsare commonly referred to as the supervisor mode and the ring-3 privilegelevel is commonly referred to as the user mode. The guest OS 118 mayassign a page mode attribute (e.g., a user mode or a supervisor mode) ofa page in the guest virtual address space.

VMs 116 including guest OS 118 and guest application 120 may accessmemory 104 through a series of memory space mappings. Guest OS 118 mayconstruct a guest virtual address (GVA) space 122 that may be mapped toa corresponding guest physical address (GPA) space 124 for a VM 116. GPAspace 124 may be organized according to guest memory pages that each hasa fixed size. Each one of the guest memory pages may be associated withan identifier that uniquely identifies the GPA page. A control register(e.g., CR3) associated with the processor 102 may contain the baseaddress of the page directory that may be used to calculate a mappingbetween the GVA space 122 and the corresponding GPA space 124.

In addition to specifying guest physical addresses, the mapping betweenthe GVA space 122 to GPA space 124 may also specify, for each virtualaddress page, certain attributes for that page as determined by theguest operating system. These attributes may include access rights thatcontrol how the resulting guest-physical address may be accessed. Anexample access right that may be specified for a virtual address page isthe page mode. The page mode may be U (user/supervisor), indicating thatthe page may be accessed by software operating in either the user modeor the supervisor mode; or S (supervisor-only), indicating that the pagemay be accessed only by software operating in the supervisor mode.

The GPA space 124 of VM 115 may be mapped to the host physical address(HPA) space of the host system 150. During execution of a guestapplication 120, responsive to a request to access memory 104, memorymanagement unit 108 may use the host physical addresses to access memory104. The HPA space may be organized according memory frames that eachhas a fixed size. Each one of the memory frames may be associated withan identifier (e.g. memory frame number) that uniquely identifies thememory frame. Processing core 106 may execute VMM 114 to create amapping from the GPA space 124 of VM 116 to the HPA space of the host.The mapping may be stored in an extended page table (EPT) 126 stored inmemory 104. In one embodiment, a policy data structure 140 stored inmemory 104 may include rules that specify how to determine the accessrights stored in EPTEs based on the corresponding page attributes (e.g.,the user mode or the supervisor mode). Thus, the VMM 114 may specifyaccess rights in an EPTE different from the access rights assigned tothe corresponding guest virtual address page by the guest OS 118. Inthis way, VMM 114 may provide a further layer of protection to a memoryframe by modifying the access rights stored in the EPTE based on rules.

VMM 114 may construct EPT 126 using EPT entries (EPTEs) that may eachspecify a mapping from an identifier of a GPA page to an identifier of amemory frame. As shown in FIG. 1, EPT 126 may include EPTEs 128 forstoring the mappings between guest memory pages and memory frames.

EPTE 128 may store one or more memory frame numbers that are associatedwith GPA page numbers. In one embodiment, guest application 120 mayallocate a block of memory by specifying one or more guest virtualaddress ranges (e.g., a number of GPA page numbers). Guest OS 118 maytranslate the guest virtual addresses in GVA space 122 into guestphysical addresses in GPA space 124. Memory management unit 108 mayemploy EPTEs 128 in EPT 126 specified by VMM 114 to map guest physicaladdresses into host physical addresses for accessing memory. In oneembodiment, memory management unit 108 may load an EPTE 128 of EPT 126into a register 110 associated with memory management unit 108 so thatthe memory management unit 108 may perform the memory address mapping onbehalf of processing cores 106.

In addition to the mapping from a guest physical address to a hostphysical address, EPTE 128 may also include fields to store certainattributes, determined by the VMM, for the guest physical address. Theseattributes may include access rights that control how the guest physicaladdress may be accessed. Example access rights include R, W, and X,indicating whether software operating in the VM may read, write, orexecute from the guest physical address, respectively.

In one embodiment of the present disclosure, the attributes specified inan EPTE for a guest physical address may depend upon the attributesspecified by the guest OS for the guest virtual address that mapped tothat guest physical address. In one embodiment, EPTE 128 may storeseveral sets of access rights flags, where each set is associated with apage mode attribute associated with the GPA. In another embodiment, EPTE128 may store sets of access right flags that each is associated with apage attribute other than the page mode. For example, EPTE 128 mayinclude a first set of access right flags (including at least one of RU,WU, or XU) that may be specified by VMM 114 to constrain requests toaccess guest virtual addresses that were mapped using the user mode anda second set of access right flags (including at least one of RS, WS, orXS) that may be specified by VMM 114 to constrain requests to accessguest virtual addresses that were mapped using the supervisor mode.

Thus, as shown in FIG. 1, EPTE 128 may include a first field 136 tostore a mapping from guest memory pages to memory frames and a secondfield 130 to store at least one access right flag 132 associated with afirst page attribute value of the guest memory pages (e.g., user mode)and at least one access right flag 134 associated with a second pageattribute of the guest memory pages (e.g., supervisor mode). Memorymanagement unit 108 may use the access right flags (132, 134) stored inEPTE 128 to constrain memory accesses.

Memory management unit 112 may include logic circuits to check thememory access rights during execution of guest applications 120 toprevent certain types of memory accesses (e.g., those caused by strayaccesses) that are not permitted by VMM 114 as specified in EPTE 128. Inone embodiment, access right flags (132, 134) stored in EPTE 128 mayinclude one or more status bits to indicate certain page access statusesthat need to be checked before accessing memory frame numbers mapped toin EPTE 128. For example, the each one of access right flags may berepresented by one bit, where an access right is enabled when the bitvalue is one (“1”) and the access right is disabled when the bit valueis zero (“0”). Thus, RU bit=1/0, indicating reads from user pages areenabled/disabled; WU bit=1/0, indicating writes to user pages areenabled/disabled; XU bit=1/0, indicating execution from user pages isenabled/disabled; RS bit=1/0, indicating reads from supervisor pages areenabled/disabled; WS bit=1/0, indicating writes to supervisor pages areenabled/disabled; XS bit=1/0, indicating execution from supervisor pagesis enabled/disabled.

The page mode, i.e., supervisor mode or user mode, is one of theattributes associated with guest memory pages accessed by guestapplication 120 running on VM 116. In one embodiment, page modeassociated with a guest virtual address may store be determined by a U/S(user/supervisor) bit that the guest operating system associates withthe page. For example, U/S bit=1 may indicate a user-mode page in theGVA space (i.e., one accessible to software operating in either usermode or in supervisor mode); U/S bit=0 may indicate supervisor-mode pagein the GVA space (i.e., one accessible only to software operating insupervisor mode).

During execution of guest application 120, memory management unit 108may receive a request including guest virtual address page numbers tomap these guest memory pages to memory frame numbers in the physicaladdress space. To speed up the memory address mapping, memory managementunit 104 may perform the memory address mapping and store the memoryaddress mapping (e.g., a mapping between a guest virtual address pagenumber to a memory frame number) in a buffer 138 (e.g., a translationlookaside buffer (TLB)) stored in processor 102. Buffer 138 may includemultiple buffer entries. Each one of the buffer entry may include afirst field to store a mapping between one guest virtual address pageand one memory frame, and a second field to store the access right flags(e.g., R, W, X) associated with the memory frame. In one embodiment,memory management unit 108 may determine which access right flags tocopy to the buffer entry based on the GPA page attribute value (e.g.,U/S bit value) of the GPA page to which the guest virtual address pagewas mapped.

In one embodiment, if the U/S bit indicates the user mode, memorymanagement unit 108 copies the first set of access right flags (RU, WU,XU) stored in field 132 of EPTE 128 to the corresponding field for R, W,and X in the buffer entry. If the U/S bit indicates supervisor mode,memory management unit 108 copies the second set of access right flags(RS, WS, XS) stored in field 134 of EPTE 128 to the corresponding fieldfor R, W, and X in the buffer entry. The TLB does not distinguish read,write, and execute access rights based on the U/S bit, and the TLB mayuse the U/S bit to deny access to supervisor pages to software operatingin user mode.

In one embodiment, the separation of access right flags according to anattribute (e.g., U/S bit) associated with guest memory pages may beenabled or disabled according to a configuration flag. In oneembodiment, the configuration flag may be stored in a control register122 (e.g., CR4) associated with processor 102. In another embodiment,the virtual machine control structure of VM 116 may include a field tostore the configuration flag. Responsive to determining that theconfiguration flag indicates an enablement (e.g., configurationflag=“1”), memory management unit 108 may selectively copy the accessright flags to TLB 138 based on the U/S bit as discussed above.Responsive to determining that the configuration flag indicates adisablement (e.g., configuration flag=“0”), memory management unit 108may copy pre-determined access right flags (e.g., R, W, and X) to theTLB 138, disregarding the U/S bit value.

FIG. 2 illustrates a flowchart to show the process 200 of memory addresstranslation according to an embodiment of the present disclosure. At202, responsive to a request by a guest application to access thememory, the guest operating system running on a processor may translatethe guest virtual addresses employed by the guest application to guestphysical addresses and determine whether the page mode of a guestvirtual address is user mode or supervisor mode (as indicated by a U/Sbit associated with the guest virtual address). The processor maygenerate an output including the GPA addresses and the U/S bit value.

At 204, a memory management unit of the processor may receive the GPAaddresses and determine whether a configuration flag indicating theexpanded EPTE is set. Responsive to determining that the configurationflag is set, at 206, the memory management unit may determine the valueof the U/S bit. If the value of the U/S bit indicates a user mode page,at 212, the memory management unit may identify the correspondingaddress mapping in the extended page table entry, and copy the addressmapping and the access right flags for a user mode page (e.g., RU, WU,XU) to the TLB entry. If the U/S bit indicates a supervisor mode page,at 210, the memory management unit may identify the address mapping inthe extended page table entry, and copy the address mapping and theaccess right flags associated with the supervisor mode (e.g., RS, WS,XS) to the TLB entry.

Responsive to determining that the configuration flag is not set, at208, the memory management unit may just copy the address mapping and apre-determined access right flags (e.g., R, W, X) to the TLB entriesdisregarding the value of U/S bit.

Although the discussion is in the context of the paging attribute ofuser/supervisor mode and the access right flags (R, W, X), embodimentsof the present disclosure may also apply to other paging attributesother than the U/S bit. FIG. 3 illustrates an extended page table 300according to an embodiment of the present disclosure. As shown in FIG.3, an EPTE 302 may include a first field 304 to store memory addressmappings between guest memory pages to memory frames. EPTE 302 mayfurther include fields 306-310 to store a number of attribute fieldsassociated with different paging attributes of the guest memory pages.For example, the guest memory pages may have P=1, N-1, N attributes(e.g., U/S bit, modified (set when a page is written to), referenced(referenced by reading or writing), present/absent (whether the page isphysically present in the memory) etc.) and H number of attribute values(e.g., H=3 for the access rights of R, W, X etc.).

As shown in FIG. 3, EPTE 302 may store the H attribute values associatedwith the attribute P=1 in field 306; . . . ; the H attribute valuesassociated with the attribute P=N-1 in field 308; the H attribute valuesassociated with the attribute P=N in field 310. Thus, the memorymanagement unit may determine the paging attribute values associatedwith guest memory pages and copy the mapping store in field 304 and theattribute values associated with the determined attributes 306-310 tothe TLB entries.

When a memory access violates the attributes as defined EPTE entries,the processor (including the memory management unit) may transitioncontrol to the VMM (e.g., by way of a “VM exit”). Such transitions mayinclude communication to the VMM about the memory access and about theaccess right(s) that were violated. Embodiments of the presentdisclosure may also communicate to the VMM the GPA paging attribute(e.g., U/S mode).

FIG. 4 is a block diagram of a method 400 to perform memory addressmapping according to an embodiment of the present disclosure. Method 400may be performed by processing logic that may include hardware (e.g.,circuitry, dedicated logic, programmable logic, microcode, etc.),software (such as instructions run on a processing device, a generalpurpose computer system, or a dedicated machine), firmware, or acombination thereof. In one embodiment, method 400 may be performed, inpart, by processing logics of processor 102 as shown in FIG. 1.

For simplicity of explanation, the method 400 is depicted and describedas a series of acts. However, acts in accordance with this disclosurecan occur in various orders and/or concurrently and with other acts notpresented and described herein. Furthermore, not all illustrated actsmay be performed to implement the method 400 in accordance with thedisclosed subject matter. In addition, those skilled in the art willunderstand and appreciate that the method 400 could alternatively berepresented as a series of interrelated states via a state diagram orevents.

Referring to FIG. 4, at 402, processor 102 may determine an attribute ofa memory page referenced by a guest physical address (GPA) associatedwith a virtual machine running on the processor. For example, theattribute value may indicate a user mode or a supervisor mode of a guestvirtual address as determined by the guest operating system operating inthe virtual machine running on the processor.

At 404, processor 102 may responsive to determining that the pagingattribute value indicates a first value, copy a memory address mappingfrom the GPA page to a memory frame of a memory and a first plurality ofaccess right flags stored in an extended page table entry (EPTE) in abuffer entry.

At 406, processor 102 may responsive to determining that the pagingattribute indicates a second value, copying the memory address mappingfrom the memory page identified by the GPA to the identifier of thememory frame and a second plurality of access right flags stored in theEPTE in the buffer, in which the processor is to allow accessing thememory frame based on the access right flags in the buffer entry.

FIG. 5A is a block diagram illustrating a micro-architecture for aprocessor 500 that implements the processing device includingheterogeneous cores in accordance with one embodiment of the disclosure.Specifically, processor 500 depicts an in-order architecture core and aregister renaming logic, out-of-order issue/execution logic to beincluded in a processor according to at least one embodiment of thedisclosure.

Processor 500 includes a front end unit 530 coupled to an executionengine unit 550, and both are coupled to a memory unit 570. Theprocessor 500 may include a reduced instruction set computing (RISC)core, a complex instruction set computing (CISC) core, a very longinstruction word (VLIW) core, or a hybrid or alternative core type. Asyet another option, processor 500 may include a special-purpose core,such as, for example, a network or communication core, compressionengine, graphics core, or the like. In one embodiment, processor 500 maybe a multi-core processor or may part of a multi-processor system.

The front end unit 530 includes a branch prediction unit 532 coupled toan instruction cache unit 534, which is coupled to an instructiontranslation lookaside buffer (TLB) 536, which is coupled to aninstruction fetch unit 538, which is coupled to a decode unit 540. Thedecode unit 540 (also known as a decoder) may decode instructions, andgenerate as an output one or more micro-operations, micro-code entrypoints, microinstructions, other instructions, or other control signals,which are decoded from, or which otherwise reflect, or are derived from,the original instructions. The decoder 540 may be implemented usingvarious different mechanisms. Examples of suitable mechanisms include,but are not limited to, look-up tables, hardware implementations,programmable logic arrays (PLAs), microcode read only memories (ROMs),etc. The instruction cache unit 534 is further coupled to the memoryunit 570. The decode unit 540 is coupled to a rename/allocator unit 552in the execution engine unit 550.

The execution engine unit 550 includes the rename/allocator unit 552coupled to a retirement unit 554 and a set of one or more schedulerunit(s) 556. The scheduler unit(s) 556 represents any number ofdifferent schedulers, including reservations stations (RS), centralinstruction window, etc. The scheduler unit(s) 556 is coupled to thephysical register file(s) unit(s) 558. Each of the physical registerfile(s) units 558 represents one or more physical register files,different ones of which store one or more different data types, such asscalar integer, scalar floating point, packed integer, packed floatingpoint, vector integer, vector floating point, etc., status (e.g., aninstruction pointer that is the address of the next instruction to beexecuted), etc. The physical register file(s) unit(s) 558 is overlappedby the retirement unit 554 to illustrate various ways in which registerrenaming and out-of-order execution may be implemented (e.g., using areorder buffer(s) and a retirement register file(s), using a futurefile(s), a history buffer(s), and a retirement register file(s); using aregister maps and a pool of registers; etc.).

In one implementation, processor 500 may be the same as processor 102described with respect to FIG. 1.

Generally, the architectural registers are visible from the outside ofthe processor or from a programmer's perspective. The registers are notlimited to any known particular type of circuit. Various different typesof registers are suitable as long as they are capable of storing andproviding data as described herein. Examples of suitable registersinclude, but are not limited to, dedicated physical registers,dynamically allocated physical registers using register renaming,combinations of dedicated and dynamically allocated physical registers,etc. The retirement unit 554 and the physical register file(s) unit(s)558 are coupled to the execution cluster(s) 560. The executioncluster(s) 560 includes a set of one or more execution units 562 and aset of one or more memory access units 564. The execution units 562 mayperform various operations (e.g., shifts, addition, subtraction,multiplication) and operate on various types of data (e.g., scalarfloating point, packed integer, packed floating point, vector integer,vector floating point).

While some embodiments may include a number of execution units dedicatedto specific functions or sets of functions, other embodiments mayinclude only one execution unit or multiple execution units that allperform all functions. The scheduler unit(s) 556, physical registerfile(s) unit(s) 558, and execution cluster(s) 560 are shown as beingpossibly plural because certain embodiments create separate pipelinesfor certain types of data/operations (e.g., a scalar integer pipeline, ascalar floating point/packed integer/packed floating point/vectorinteger/vector floating point pipeline, and/or a memory access pipelinethat each have their own scheduler unit, physical register file(s) unit,and/or execution cluster—and in the case of a separate memory accesspipeline, certain embodiments are implemented in which only theexecution cluster of this pipeline has the memory access unit(s) 564).It should also be understood that where separate pipelines are used, oneor more of these pipelines may be out-of-order issue/execution and therest in-order.

The set of memory access units 564 is coupled to the memory unit 570,which may include a data prefetcher 580, a data TLB unit 572, a datacache unit (DCU) 574, and a level 2 (L2) cache unit 576, to name a fewexamples. In some embodiments DCU 574 is also known as a first leveldata cache (L1 cache). The DCU 574 may handle multiple outstanding cachemisses and continue to service incoming stores and loads. It alsosupports maintaining cache coherency. The data TLB unit 572 is a cacheused to improve virtual address translation speed by mapping virtual andphysical address spaces. In one exemplary embodiment, the memory accessunits 564 may include a load unit, a store address unit, and a storedata unit, each of which is coupled to the data TLB unit 572 in thememory unit 570. The L2 cache unit 576 may be coupled to one or moreother levels of cache and eventually to a main memory.

In one embodiment, the data prefetcher 580 speculativelyloads/prefetches data to the DCU 574 by automatically predicting whichdata a program is about to consume. Prefeteching may refer totransferring data stored in one memory location of a memory hierarchy(e.g., lower level caches or memory) to a higher-level memory locationthat is closer (e.g., yields lower access latency) to the processorbefore the data is actually demanded by the processor. Morespecifically, prefetching may refer to the early retrieval of data fromone of the lower level caches/memory to a data cache and/or prefetchbuffer before the processor issues a demand for the specific data beingreturned.

The processor 500 may support one or more instructions sets (e.g., thex86 instruction set (with some extensions that have been added withnewer versions); the MIPS instruction set of MIPS Technologies ofSunnyvale, CA; the ARM instruction set (with optional additionalextensions such as NEON) of ARM Holdings of Sunnyvale, CA).

It should be understood that the core may support multithreading(executing two or more parallel sets of operations or threads), and maydo so in a variety of ways including time sliced multithreading,simultaneous multithreading (where a single physical core provides alogical core for each of the threads that physical core issimultaneously multithreading), or a combination thereof (e.g., timesliced fetching and decoding and simultaneous multithreading thereaftersuch as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-orderexecution, it should be understood that register renaming may be used inan in-order architecture. While the illustrated embodiment of theprocessor also includes a separate instruction and data cache units anda shared L2 cache unit, alternative embodiments may have a singleinternal cache for both instructions and data, such as, for example, aLevel 1 (L1) internal cache, or multiple levels of internal cache. Insome embodiments, the system may include a combination of an internalcache and an external cache that is external to the core and/or theprocessor. Alternatively, all of the cache may be external to the coreand/or the processor.

FIG. 5B is a block diagram illustrating an in-order pipeline and aregister renaming stage, out-of-order issue/execution pipelineimplemented by processing device 500 of FIG. 5A according to someembodiments of the disclosure. The solid lined boxes in FIG. 5Billustrate an in-order pipeline, while the dashed lined boxesillustrates a register renaming, out-of-order issue/execution pipeline.In FIG. 5B, a processor pipeline 500 includes a fetch stage 502, alength decode stage 504, a decode stage 506, an allocation stage 508, arenaming stage 510, a scheduling (also known as a dispatch or issue)stage 512, a register read/memory read stage 514, an execute stage 516,a write back/memory write stage 518, an exception handling stage 522,and a commit stage 524. In some embodiments, the ordering of stages502-524 may be different than illustrated and are not limited to thespecific ordering shown in FIG. 5B.

FIG. 6 illustrates a block diagram of the micro-architecture for aprocessor 600 that includes hybrid cores in accordance with oneembodiment of the disclosure. In some embodiments, an instruction inaccordance with one embodiment can be implemented to operate on dataelements having sizes of byte, word, doubleword, quadword, etc., as wellas datatypes, such as single and double precision integer and floatingpoint datatypes. In one embodiment the in-order front end 601 is thepart of the processor 600 that fetches instructions to be executed andprepares them to be used later in the processor pipeline.

The front end 601 may include several units. In one embodiment, theinstruction prefetcher 626 fetches instructions from memory and feedsthem to an instruction decoder 628 which in turn decodes or interpretsthem. For example, in one embodiment, the decoder decodes a receivedinstruction into one or more operations called “micro-instructions” or“micro-operations” (also called micro op or uops) that the machine canexecute. In other embodiments, the decoder parses the instruction intoan opcode and corresponding data and control fields that are used by themicro-architecture to perform operations in accordance with oneembodiment. In one embodiment, the trace cache 630 takes decoded uopsand assembles them into program ordered sequences or traces in the uopqueue 634 for execution. When the trace cache 630 encounters a complexinstruction, the microcode ROM 632 provides the uops needed to completethe operation.

Some instructions are converted into a single micro-op, whereas othersneed several micro-ops to complete the full operation. In oneembodiment, if more than four micro-ops are needed to complete aninstruction, the decoder 628 accesses the microcode ROM 632 to do theinstruction. For one embodiment, an instruction can be decoded into asmall number of micro ops for processing at the instruction decoder 628.In another embodiment, an instruction can be stored within the microcodeROM 632 should a number of micro-ops be needed to accomplish theoperation. The trace cache 630 refers to an entry point programmablelogic array (PLA) to determine a correct micro-instruction pointer forreading the micro-code sequences to complete one or more instructions inaccordance with one embodiment from the micro-code ROM 632. After themicrocode ROM 632 finishes sequencing micro-ops for an instruction, thefront end 601 of the machine resumes fetching micro-ops from the tracecache 630.

The out-of-order execution engine 603 is where the instructions areprepared for execution. The out-of-order execution logic has a number ofbuffers to smooth out and re-order the flow of instructions to optimizeperformance as they go down the pipeline and get scheduled forexecution. The allocator logic allocates the machine buffers andresources that each uop needs in order to execute. The register renaminglogic renames logic registers onto entries in a register file. Theallocator also allocates an entry for each uop in one of the two uopqueues, one for memory operations and one for non-memory operations, infront of the instruction schedulers: memory scheduler, fast scheduler602, slow/general floating point scheduler 604, and simple floatingpoint scheduler 606. The uop schedulers 602, 604, 606, determine when auop is ready to execute based on the readiness of their dependent inputregister operand sources and the availability of the execution resourcesthe uops need to complete their operation. The fast scheduler 602 of oneembodiment can schedule on each half of the main clock cycle while theother schedulers can only schedule once per main processor clock cycle.The schedulers arbitrate for the dispatch ports to schedule uops forexecution.

Register files 608, 610, sit between the schedulers 602, 604, 606, andthe execution units 612, 614, 616, 618, 620, 622, 624 in the executionblock 611. There is a separate register file 608, 610, for integer andfloating point operations, respectively. Each register file 608, 610, ofone embodiment also includes a bypass network that can bypass or forwardjust completed results that have not yet been written into the registerfile to new dependent uops. The integer register file 608 and thefloating point register file 610 are also capable of communicating datawith the other. For one embodiment, the integer register file 608 issplit into two separate register files, one register file for the loworder 32 bits of data and a second register file for the high order 32bits of data. The floating point register file 610 of one embodiment has128 bit wide entries because floating point instructions typically haveoperands from 64 to 128 bits in width.

The execution block 611 contains the execution units 612, 614, 616, 618,620, 622, 624, where the instructions are actually executed. Thissection includes the register files 608, 610, that store the integer andfloating point data operand values that the micro-instructions need toexecute. The processor 600 of one embodiment is comprised of a number ofexecution units: address generation unit (AGU) 612, AGU 614, fast ALU616, fast ALU 618, slow ALU 620, floating point ALU 622, floating pointmove unit 624. For one embodiment, the floating point execution blocks622, 624, execute floating point, MMX, SIMD, and SSE, or otheroperations. The floating point ALU 622 of one embodiment includes a 64bit by 64 bit floating point divider to execute divide, square root, andremainder micro-ops. For embodiments of the present disclosure,instructions involving a floating point value may be handled with thefloating point hardware.

In one embodiment, the ALU operations go to the high-speed ALU executionunits 616, 618. The fast ALUs 616, 618, of one embodiment can executefast operations with an effective latency of half a clock cycle. For oneembodiment, most complex integer operations go to the slow ALU 620 asthe slow ALU 620 includes integer execution hardware for long latencytype of operations, such as a multiplier, shifts, flag logic, and branchprocessing. Memory load/store operations are executed by the AGUs 612,614. For one embodiment, the integer ALUs 616, 618, 620, are describedin the context of performing integer operations on 64 bit data operands.In alternative embodiments, the ALUs 616, 618, 620, can be implementedto support a variety of data bits including 16, 32, 128, 256, etc.Similarly, the floating point units 622, 624, can be implemented tosupport a range of operands having bits of various widths. For oneembodiment, the floating point units 622, 624, can operate on 128 bitswide packed data operands in conjunction with SIMD and multimediainstructions.

In one embodiment, the uops schedulers 602, 604, 606, dispatch dependentoperations before the parent load has finished executing. As uops arespeculatively scheduled and executed in processor 600, the processor 600also includes logic to handle memory misses. If a data load misses inthe data cache, there can be dependent operations in flight in thepipeline that have left the scheduler with temporarily incorrect data. Areplay mechanism tracks and re-executes instructions that use incorrectdata. Only the dependent operations need to be replayed and theindependent ones are allowed to complete. The schedulers and replaymechanism of one embodiment of a processor are also designed to catchinstruction sequences for text string comparison operations.

The processor 600 also includes logic to implement store addressprediction for memory disambiguation according to embodiments of thedisclosure. In one embodiment, the execution block 611 of processor 600may include a store address predictor (not shown) for implementing storeaddress prediction for memory disambiguation.

The term “registers” may refer to the on-board processor storagelocations that are used as part of instructions to identify operands. Inother words, registers may be those that are usable from the outside ofthe processor (from a programmer's perspective). However, the registersof an embodiment should not be limited in meaning to a particular typeof circuit. Rather, a register of an embodiment is capable of storingand providing data, and performing the functions described herein. Theregisters described herein can be implemented by circuitry within aprocessor using any number of different techniques, such as dedicatedphysical registers, dynamically allocated physical registers usingregister renaming, combinations of dedicated and dynamically allocatedphysical registers, etc. In one embodiment, integer registers storethirty-two bit integer data. A register file of one embodiment alsocontains eight multimedia SIMD registers for packed data.

For the discussions below, the registers are understood to be dataregisters designed to hold packed data, such as 64 bits wide MMXTMregisters (also referred to as ‘mm’ registers in some instances) inmicroprocessors enabled with MMX technology from Intel Corporation ofSanta Clara, Calif. These MMX registers, available in both integer andfloating point forms, can operate with packed data elements thataccompany SIMD and SSE instructions. Similarly, 128 bits wide XMMregisters relating to SSE2, SSE3, SSE4, or beyond (referred togenerically as “SSEx”) technology can also be used to hold such packeddata operands. In one embodiment, in storing packed data and integerdata, the registers do not need to differentiate between the two datatypes. In one embodiment, integer and floating point are eithercontained in the same register file or different register files.Furthermore, in one embodiment, floating point and integer data may bestored in different registers or the same registers.

Referring now to FIG. 7, shown is a block diagram illustrating a system700 in which an embodiment of the disclosure may be used. As shown inFIG. 7, multiprocessor system 700 is a point-to-point interconnectsystem, and includes a first processor 770 and a second processor 780coupled via a point-to-point interconnect 750. While shown with only twoprocessors 770, 780, it is to be understood that the scope ofembodiments of the disclosure is not so limited. In other embodiments,one or more additional processors may be present in a given processor.In one embodiment, the multiprocessor system 700 may implement hybridcores as described herein.

Processors 770 and 780 are shown including integrated memory controllerunits 772 and 782, respectively. Processor 770 also includes as part ofits bus controller units point-to-point (P-P) interfaces 776 and 778;similarly, second processor 780 includes P-P interfaces 786 and 788.Processors 770, 780 may exchange information via a point-to-point (P-P)interface 750 using P-P interface circuits 778, 788. As shown in FIG. 7,IMCs 772 and 782 couple the processors to respective memories, namely amemory 732 and a memory 734, which may be portions of main memorylocally attached to the respective processors.

Processors 770, 780 may each exchange information with a chipset 790 viaindividual P-P interfaces 752, 754 using point to point interfacecircuits 776, 794, 786, 798. Chipset 790 may also exchange informationwith a high-performance graphics circuit 738 via a high-performancegraphics interface 739.

A shared cache (not shown) may be included in either processor oroutside of both processors, yet connected with the processors via P-Pinterconnect, such that either or both processors' local cacheinformation may be stored in the shared cache if a processor is placedinto a low power mode.

Chipset 790 may be coupled to a first bus 716 via an interface 796. Inone embodiment, first bus 716 may be a Peripheral Component Interconnect(PCI) bus, or a bus such as a PCI Express bus or another thirdgeneration I/O interconnect bus, although the scope of the presentdisclosure is not so limited.

As shown in FIG. 7, various I/O devices 714 may be coupled to first bus716, along with a bus bridge 718 which couples first bus 716 to a secondbus 720. In one embodiment, second bus 720 may be a low pin count (LPC)bus. Various devices may be coupled to second bus 720 including, forexample, a keyboard and/or mouse 722, communication devices 727 and astorage unit 728 such as a disk drive or other mass storage device whichmay include instructions/code and data 730, in one embodiment. Further,an audio I/O 724 may be coupled to second bus 720. Note that otherarchitectures are possible. For example, instead of the point-to-pointarchitecture of FIG. 7, a system may implement a multi-drop bus or othersuch architecture.

Referring now to FIG. 8, shown is a block diagram of a system 800 inwhich one embodiment of the disclosure may operate. The system 800 mayinclude one or more processors 810, 815, which are coupled to graphicsmemory controller hub (GMCH) 820. The optional nature of additionalprocessors 815 is denoted in FIG. 8 with broken lines. In oneembodiment, processors 810, 815 implement hybrid cores according toembodiments of the disclosure.

Each processor 810, 815 may be some version of the circuit, integratedcircuit, processor, and/or silicon integrated circuit as describedabove. However, it should be noted that it is unlikely that integratedgraphics logic and integrated memory control units would exist in theprocessors 810, 815. FIG. 8 illustrates that the GMCH 820 may be coupledto a memory 840 that may be, for example, a dynamic random access memory(DRAM). The DRAM may, for at least one embodiment, be associated with anon-volatile cache.

The GMCH 820 may be a chipset, or a portion of a chipset. The GMCH 820may communicate with the processor(s) 810, 815 and control interactionbetween the processor(s) 810, 815 and memory 840. The GMCH 820 may alsoact as an accelerated bus interface between the processor(s) 810, 815and other elements of the system 800. For at least one embodiment, theGMCH 820 communicates with the processor(s) 810, 815 via a multi-dropbus, such as a frontside bus (FSB) 895.

Furthermore, GMCH 820 is coupled to a display 845 (such as a flat panelor touchscreen display). GMCH 820 may include an integrated graphicsaccelerator. GMCH 820 is further coupled to an input/output (I/O)controller hub (ICH) 850, which may be used to couple various peripheraldevices to system 800. Shown for example in the embodiment of FIG. 8 isan external graphics device 860, which may be a discrete graphicsdevice, coupled to ICH 850, along with another peripheral device 870.

Alternatively, additional or different processors may also be present inthe system 800. For example, additional processor(s) 815 may includeadditional processors(s) that are the same as processor 810, additionalprocessor(s) that are heterogeneous or asymmetric to processor 810,accelerators (such as, e.g., graphics accelerators or digital signalprocessing (DSP) units), field programmable gate arrays, or any otherprocessor. There can be a variety of differences between theprocessor(s) 810, 815 in terms of a spectrum of metrics of meritincluding architectural, micro-architectural, thermal, power consumptioncharacteristics, and the like. These differences may effectivelymanifest themselves as asymmetry and heterogeneity amongst theprocessors 810, 815. For at least one embodiment, the various processors810, 815 may reside in the same die package.

Referring now to FIG. 9, shown is a block diagram of a system 900 inwhich an embodiment of the disclosure may operate. FIG. 9 illustratesprocessors 970, 980. In one embodiment, processors 970, 980 mayimplement hybrid cores as described above. Processors 970, 980 mayinclude integrated memory and I/O control logic (“CL”) 972 and 982,respectively and intercommunicate with each other via point-to-pointinterconnect 950 between point-to-point (P-P) interfaces 978 and 988respectively. Processors 970, 980 each communicate with chipset 990 viapoint-to-point interconnects 952 and 954 through the respective P-Pinterfaces 976 to 994 and 986 to 998 as shown. For at least oneembodiment, the CL 972, 982 may include integrated memory controllerunits. CLs 972, 982 may include I/O control logic. As depicted, memories932, 934 coupled to CLs 972, 982 and I/O devices 914 are also coupled tothe control logic 972, 982. Legacy I/O devices 915 are coupled to thechipset 990 via interface 996.

Embodiments may be implemented in many different system types. FIG. 10is a block diagram of a SoC 1000 in accordance with an embodiment of thepresent disclosure. Dashed lined boxes are optional features on moreadvanced SoCs. In FIG. 10, an interconnect unit(s) 1012 is coupled to:an application processor 1020 which includes a set of one or more cores1002A-N and shared cache unit(s) 1006; a system agent unit 1010; a buscontroller unit(s) 1016; an integrated memory controller unit(s) 1014; aset or one or more media processors 1018 which may include integratedgraphics logic 1008, an image processor 1024 for providing still and/orvideo camera functionality, an audio processor 1026 for providinghardware audio acceleration, and a video processor 1028 for providingvideo encode/decode acceleration; an static random access memory (SRAM)unit 1030; a direct memory access (DMA) unit 1032; and a display unit1040 for coupling to one or more external displays. In one embodiment, amemory module may be included in the integrated memory controllerunit(s) 1014. In another embodiment, the memory module may be includedin one or more other components of the SoC 1000 that may be used toaccess and/or control a memory. The application processor 1020 mayinclude a store address predictor for implementing hybrid cores asdescribed in embodiments herein.

The memory hierarchy includes one or more levels of cache within thecores, a set or one or more shared cache units 1006, and external memory(not shown) coupled to the set of integrated memory controller units1014. The set of shared cache units 1006 may include one or moremid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), orother levels of cache, a last level cache (LLC), and/or combinationsthereof.

In some embodiments, one or more of the cores 1002A-N are capable ofmulti-threading. The system agent 1010 includes those componentscoordinating and operating cores 1002A-N. The system agent unit 1010 mayinclude for example a power control unit (PCU) and a display unit. ThePCU may be or include logic and components needed for regulating thepower state of the cores 1002A-N and the integrated graphics logic 1008.The display unit is for driving one or more externally connecteddisplays.

The cores 1002A-N may be homogenous or heterogeneous in terms ofarchitecture and/or instruction set. For example, some of the cores1002A-N may be in order while others are out-of-order. As anotherexample, two or more of the cores 1002A-N may be capable of executionthe same instruction set, while others may be capable of executing onlya subset of that instruction set or a different instruction set.

The application processor 1020 may be a general-purpose processor, suchas a Core™ i3, i5, i7, 2 Duo and Quad, Xeon™, Itanium™, Atom™ or Quark™processor, which are available from Intel™ Corporation, of Santa Clara,Calif. Alternatively, the application processor 1020 may be from anothercompany, such as ARM Holdings™, Ltd, MIPS™, etc. The applicationprocessor 1020 may be a special-purpose processor, such as, for example,a network or communication processor, compression engine, graphicsprocessor, co-processor, embedded processor, or the like. Theapplication processor 1020 may be implemented on one or more chips. Theapplication processor 1020 may be a part of and/or may be implemented onone or more substrates using any of a number of process technologies,such as, for example, BiCMOS, CMOS, or NMOS.

FIG. 11 is a block diagram of an embodiment of a system on-chip (SoC)design in accordance with the present disclosure. As a specificillustrative example, SoC 1100 is included in user equipment (UE). Inone embodiment, UE refers to any device to be used by an end-user tocommunicate, such as a hand-held phone, smartphone, tablet, ultra-thinnotebook, notebook with broadband adapter, or any other similarcommunication device. Often a UE connects to a base station or node,which potentially corresponds in nature to a mobile station (MS) in aGSM network.

Here, SOC 1100 includes 2 cores-1106 and 1107. Cores 1106 and 1107 mayconform to an Instruction Set Architecture, such as an Intel®Architecture Core™-based processor, an Advanced Micro Devices, Inc.(AMD) processor, a MIPS-based processor, an ARM-based processor design,or a customer thereof, as well as their licensees or adopters. Cores1106 and 1107 are coupled to cache control 1108 that is associated withbus interface unit 1109 and L2 cache 1110 to communicate with otherparts of system 1100. Interconnect 1110 includes an on-chipinterconnect, such as an IOSF, AMBA, or other interconnect discussedabove, which potentially implements one or more aspects of the describeddisclosure. In one embodiment, cores 1106, 1107 may implement hybridcores as described in embodiments herein.

Interconnect 1110 provides communication channels to the othercomponents, such as a Subscriber Identity Module (SIM) 1130 to interfacewith a SIM card, a boot ROM 1135 to hold boot code for execution bycores 1106 and 1107 to initialize and boot SoC 1100, a SDRAM controller1140 to interface with external memory (e.g. DRAM 1160), a flashcontroller 1145 to interface with non-volatile memory (e.g. Flash 1165),a peripheral control 1150 (e.g. Serial Peripheral Interface) tointerface with peripherals, video codecs 1120 and Video interface 1125to display and receive input (e.g. touch enabled input), GPU 1115 toperform graphics related computations, etc. Any of these interfaces mayincorporate aspects of the disclosure described herein. In addition, thesystem 1100 illustrates peripherals for communication, such as aBluetooth module 1170, 3G modem 1175, GPS 1180, and Wi-Fi 1185.

FIG. 12 illustrates a diagrammatic representation of a machine in theexample form of a computer system 1200 within which a set ofinstructions, for causing the machine to perform any one or more of themethodologies discussed herein, may be executed. In alternativeembodiments, the machine may be connected (e.g., networked) to othermachines in a LAN, an intranet, an extranet, or the Internet. Themachine may operate in the capacity of a server or a client device in aclient-server network environment, or as a peer machine in apeer-to-peer (or distributed) network environment. The machine may be apersonal computer (PC), a tablet PC, a set-top box (STB), a PersonalDigital Assistant (PDA), a cellular telephone, a web appliance, aserver, a network router, switch or bridge, or any machine capable ofexecuting a set of instructions (sequential or otherwise) that specifyactions to be taken by that machine. Further, while only a singlemachine is illustrated, the term “machine” shall also be taken toinclude any collection of machines that individually or jointly executea set (or multiple sets) of instructions to perform any one or more ofthe methodologies discussed herein.

The computer system 1200 includes a processing device 1202, a mainmemory 1204 (e.g., read-only memory (ROM), flash memory, dynamic randomaccess memory (DRAM) (such as synchronous DRAM (SDRAM) or DRAM (RDRAM),etc.), a static memory 1206 (e.g., flash memory, static random accessmemory (SRAM), etc.), and a data storage device 1218, which communicatewith each other via a bus 1230.

Processing device 1202 represents one or more general-purpose processingdevices such as a microprocessor, central processing unit, or the like.More particularly, the processing device may be complex instruction setcomputing (CISC) microprocessor, reduced instruction set computer (RISC)microprocessor, very long instruction word (VLIW) microprocessor, orprocessor implementing other instruction sets, or processorsimplementing a combination of instruction sets. Processing device 1202may also be one or more special-purpose processing devices such as anapplication specific integrated circuit (ASIC), a field programmablegate array (FPGA), a digital signal processor (DSP), network processor,or the like. In one embodiment, processing device 1202 may include oneor processing cores. The processing device 1202 is configured to executethe processing logic 1226 for performing the operations and stepsdiscussed herein. In one embodiment, processing device 1202 is the sameas processor architecture 100 described with respect to FIG. 1 asdescribed herein with embodiments of the disclosure.

The computer system 1200 may further include a network interface device1208 communicably coupled to a network 1220. The computer system 1200also may include a video display unit 1210 (e.g., a liquid crystaldisplay (LCD) or a cathode ray tube (CRT)), an alphanumeric input device1212 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse),and a signal generation device 1216 (e.g., a speaker). Furthermore,computer system 1200 may include a graphics processing unit 1222, avideo processing unit 1228, and an audio processing unit 1232.

The data storage device 1218 may include a machine-accessible storagemedium 1224 on which is stored software 1226 implementing any one ormore of the methodologies of functions described herein, such asimplementing store address prediction for memory disambiguation asdescribed above. The software 1226 may also reside, completely or atleast partially, within the main memory 1204 as instructions 1226 and/orwithin the processing device 1202 as processing logic 1226 duringexecution thereof by the computer system 1200; the main memory 1204 andthe processing device 1202 also constituting machine-accessible storagemedia.

The machine-readable storage medium 1224 may also be used to storeinstructions 1226 implementing store address prediction for hybrid coressuch as described according to embodiments of the disclosure. While themachine-accessible storage medium 1128 is shown in an example embodimentto be a single medium, the term “machine-accessible storage medium”should be taken to include a single medium or multiple media (e.g., acentralized or distributed database, and/or associated caches andservers) that store the one or more sets of instructions. The term“machine-accessible storage medium” shall also be taken to include anymedium that is capable of storing, encoding or carrying a set ofinstruction for execution by the machine and that cause the machine toperform any one or more of the methodologies of the present disclosure.The term “machine-accessible storage medium” shall accordingly be takento include, but not be limited to, solid-state memories, and optical andmagnetic media.

The following examples pertain to further embodiments. Example 1 is aprocessing system including a processing core to execute a virtualmachine (VM) comprising a guest operating system (OS) and a memorymanagement unit, communicatively coupled to the processing core,comprising a storage device to store an extended page table entry (EPTE)comprising a mapping from a guest physical address (GPA) associated withthe guest OS to an identifier of a memory frame, a first plurality ofaccess right flags associated with accessing the memory frame in a firstpage mode referenced by an attribute of a memory page identified by theGPA, and a second plurality of access right flags associated withaccessing the memory frame in a second page mode referenced by theattribute of the memory page identified by the GPA, wherein the memorymanagement unit is to responsive to determining that the GPA isassociated with the first page mode, allow accessing the memory framebased on the first plurality of access right flags; and responsive todetermining that the GPA is associated with the second page mode, allowaccessing the memory frame based on the second plurality of access rightflags.

In Example 2, the subject matter of Example 1 can optionally providethat the processing core is further to execute a virtual machine monitor(VMM) to support the VM, wherein the VMM is to specify the firstplurality of access right flags and the second plurality of access rightflags stored in the EPTE based on a plurality of rules stored in apolicy data structure.

In Example 3, the subject matter of any of Examples 1 and 2 canoptionally provide that the first page mode of the GPA is a user modeassigned to a corresponding guest virtual address (GVA) by the guest OSand the second page mode of the GPA is a supervisor mode assigned to thecorresponding GVA by the guest OS.

In Example 4, the subject matter of Example 3 can optionally providethat the first plurality of access right flags comprises at least one ofa read access flag, a write access flag, or an execute access flag.

In Example 5, the subject matter of Example 3 can optionally providethat the second plurality of access right flags comprises at least oneof a read access flag, a write access flag, or an execute access flag.

In Example 6, the subject matter of Example 3 can optionally providethat responsive to determining that a user/supervisor (U/S) status flagindicates the user mode, store the mapping and the first plurality ofaccess right flags in a buffer entry, and responsive to determining thatthe U/S status flag indicates the supervisor mode, store the mapping andthe second plurality of access right flags in the buffer entry.

In Example 7, the subject matter of Example 6 can optionally providethat the buffer entry is a translation lookaside buffer (TLB) entryassociated with the processing system.

In Example 8, the subject matter of Example 6 can optionally providethat responsive to detecting a memory access violation based on one ofthe first plurality of access right flags or the second plurality ofaccess right flags, communicate, to the VMM, the GPA and an access rightthat is violated.

In Example 9, the subject matter of Example 1 can optionally providethat the first attribute value is associated with a memory frame presentattribute, and the second attribute value is associated with a memoryframe absent attribute.

Example 10 is a system-on-a-chip (SoC) comprising a memory to store anextended page table entry (EPTE), and a processor, communicativelycoupled to the memory, comprising a processing core to execute a virtualmachine (VM) comprising a guest operating system (OS), and a memorymanagement unit, communicatively coupled to the processing core,comprising a storage device to store the EPTE comprising a mapping froma guest physical address (GPA) associated with the guest OS to anidentifier of a memory frame, a first plurality of access right flagsassociated with accessing the memory frame in a first page modereferenced by an attribute of a memory page identified by the GPA, and asecond plurality of access right flags associated with accessing thememory frame in a second page mode referenced by the attribute of thememory page identified by the GPA, wherein the memory management unit isto responsive to determining that the GPA is associated with the firstpage mode, allow accessing the memory frame based on the first pluralityof access right flags and responsive to determining that the GPA isassociated with the second page mode, allow accessing the memory framebased on the second plurality of access right flags.

In Example 11, the subject matter of Example 10 can optionally providethat execute a virtual machine monitor (VMM) to support the VM, whereinthe VMM is to specify the first plurality of access right flags and thesecond plurality of access right flags stored in the EPTE based on aplurality of rules stored in a policy data structure.

In Example 12, the subject matter of any of Examples 10 and 11 canoptionally provide that the first page mode of the GPA is a user modeassigned to a corresponding guest virtual address (GVA) by the guest OSand the second page mode of the GPA is a supervisor mode assigned to thecorresponding GVA by the guest OS.

In Example 13, the subject matter of Example 12 can optionally providethat the first plurality of access right flags comprises at least one ofa read access flag, a write access flag, or an execute access flag.

In Example 14, the subject matter of Example 12 can optionally providethat the second plurality of access right flags comprises at least oneof a read access flag, a write access flag, or an execute access flag.

In Example 15, the subject matter of Example 12 can optionally providethat the memory management unit is to responsive to determining that auser/supervisor (U/S) status flag indicates the user mode, store themapping and the first plurality of access right flags in a buffer entry,and responsive to determining that the U/S status flag indicates thesupervisor mode, store the mapping and the second plurality of accessright flags in the buffer entry.

In Example 16, the subject matter of Example 15 can optionally providethat the memory management unit is further to responsive to detecting amemory access violation based on one of the first plurality of accessright flags or the second plurality of access right flags, communicateto the VMM the GPA and an access right that is violated.

In Example 17, the subject matter of Example 10 can optionally providethat the first attribute value is associated with a memory frame presentattribute, and the second attribute value is associated with a memoryframe absent attribute.

Example 18 is a method comprising determining, by a processor, anattribute of a memory page referenced by a guest physical address (GPA)associated with a virtual machine running on the processor, responsiveto determining that the attribute indicates a first page mode, copying amemory address mapping from a memory page identified by the GPA to anidentifier of a memory frame and a first plurality of access right flagsstored in an extended page table entry (EPTE) in a buffer, andresponsive to determining that the paging attribute indicates a secondpage mode, copying the memory address mapping from the memory pageidentified by the GPA to the identifier of the memory frame and a secondplurality of access right flags stored in the EPTE in the buffer,wherein the processor is to allow accessing the memory frame based onthe access right flags in the buffer entry.

In Example 19, the subject matter of Example 18 can optionally providethat the processor is further to execute a virtual machine monitor (VMM)to support the VM, wherein the VMM is to specify the first plurality ofaccess right flags and the second plurality of access right flags storedin the EPTE.

In Example 20, the subject matter of any of Examples 18 and 19 canoptionally provide that the first page mode of the GPA is a user modeassigned to a corresponding guest virtual address (GVA) by the guest OSand the second page mode of the GPA is a supervisor mode assigned to thecorresponding GVA by the guest OS.

Example 21 is an apparatus including means for performing the method ofany of Examples 18 and 19.

Example 22 is a machine-readable non-transitory medium having storedthereon program code that, when executed by a processor, performoperations comprising determining, by the processor, an attribute of amemory page referenced by a guest physical address (GPA) associated witha virtual machine running on the processor, responsive to determiningthat the attribute indicates a first page mode, copying a memory addressmapping from a memory page referenced by the GPA to an identifier of amemory frame and a first plurality of access right flags stored in anextended page table entry (EPTE) in a buffer, and responsive todetermining that the paging attribute indicates a second page mode,copying the memory address mapping from the memory page referenced bythe GPA to the identifier of the memory frame and a second plurality ofaccess right flags stored in the EPTE in the buffer, wherein theprocessor is to allow accessing the memory frame based on the accessright flags in the buffer entry.

In Example 23, the subject matter of Example 22 can optionally providethat the operations further comprises executing a virtual machinemonitor (VMM) to support the VM, wherein the VMM is to specify the firstplurality of access right flags and the second plurality of access rightflags stored in the EPTE.

In Example 24, the subject matter of Examples 22 and 23 can optionallyprovide that the first page mode of the GPA is a user mode assigned to acorresponding guest virtual address (GVA) by the guest OS and the secondpage mode of the GPA is a supervisor mode assigned to the correspondingGVA by the guest OS.

While the disclosure has been described with respect to a limited numberof embodiments, those skilled in the art will appreciate numerousmodifications and variations there from. It is intended that theappended claims cover all such modifications and variations as fallwithin the true spirit and scope of this disclosure.

A design may go through various stages, from creation to simulation tofabrication. Data representing a design may represent the design in anumber of manners. First, as is useful in simulations, the hardware maybe represented using a hardware description language or anotherfunctional description language. Additionally, a circuit level modelwith logic and/or transistor gates may be produced at some stages of thedesign process. Furthermore, most designs, at some stage, reach a levelof data representing the physical placement of various devices in thehardware model. In the case where conventional semiconductor fabricationtechniques are used, the data representing the hardware model may be thedata specifying the presence or absence of various features on differentmask layers for masks used to produce the integrated circuit. In anyrepresentation of the design, the data may be stored in any form of amachine readable medium. A memory or a magnetic or optical storage suchas a disc may be the machine readable medium to store informationtransmitted via optical or electrical wave modulated or otherwisegenerated to transmit such information. When an electrical carrier waveindicating or carrying the code or design is transmitted, to the extentthat copying, buffering, or re-transmission of the electrical signal isperformed, a new copy is made. Thus, a communication provider or anetwork provider may store on a tangible, machine-readable medium, atleast temporarily, an article, such as information encoded into acarrier wave, embodying techniques of embodiments of the presentdisclosure.

A module as used herein refers to any combination of hardware, software,and/or firmware. As an example, a module includes hardware, such as amicro-controller, associated with a non-transitory medium to store codeadapted to be executed by the micro-controller. Therefore, reference toa module, in one embodiment, refers to the hardware, which isspecifically configured to recognize and/or execute the code to be heldon a non-transitory medium. Furthermore, in another embodiment, use of amodule refers to the non-transitory medium including the code, which isspecifically adapted to be executed by the microcontroller to performpredetermined operations. And as can be inferred, in yet anotherembodiment, the term module (in this example) may refer to thecombination of the microcontroller and the non-transitory medium. Oftenmodule boundaries that are illustrated as separate commonly vary andpotentially overlap. For example, a first and a second module may sharehardware, software, firmware, or a combination thereof, whilepotentially retaining some independent hardware, software, or firmware.In one embodiment, use of the term logic includes hardware, such astransistors, registers, or other hardware, such as programmable logicdevices.

Use of the phrase ‘configured to,’ in one embodiment, refers toarranging, putting together, manufacturing, offering to sell, importingand/or designing an apparatus, hardware, logic, or element to perform adesignated or determined task. In this example, an apparatus or elementthereof that is not operating is still ‘configured to’ perform adesignated task if it is designed, coupled, and/or interconnected toperform said designated task. As a purely illustrative example, a logicgate may provide a 0 or a 1 during operation. But a logic gate‘configured to’ provide an enable signal to a clock does not includeevery potential logic gate that may provide a 1 or 0. Instead, the logicgate is one coupled in some manner that during operation the 1 or 0output is to enable the clock. Note once again that use of the term‘configured to’ does not require operation, but instead focus on thelatent state of an apparatus, hardware, and/or element, where in thelatent state the apparatus, hardware, and/or element is designed toperform a particular task when the apparatus, hardware, and/or elementis operating.

Furthermore, use of the phrases ‘to,’ ‘capable of/to,’ and or ‘operableto,’ in one embodiment, refers to some apparatus, logic, hardware,and/or element designed in such a way to enable use of the apparatus,logic, hardware, and/or element in a specified manner. Note as abovethat use of to, capable to, or operable to, in one embodiment, refers tothe latent state of an apparatus, logic, hardware, and/or element, wherethe apparatus, logic, hardware, and/or element is not operating but isdesigned in such a manner to enable use of an apparatus in a specifiedmanner.

A value, as used herein, includes any known representation of a number,a state, a logical state, or a binary logical state. Often, the use oflogic levels, logic values, or logical values is also referred to as 1'sand 0's, which simply represents binary logic states. For example, a 1refers to a high logic level and 0 refers to a low logic level. In oneembodiment, a storage cell, such as a transistor or flash cell, may becapable of holding a single logical value or multiple logical values.However, other representations of values in computer systems have beenused. For example the decimal number ten may also be represented as abinary value of 910 and a hexadecimal letter A. Therefore, a valueincludes any representation of information capable of being held in acomputer system.

Moreover, states may be represented by values or portions of values. Asan example, a first value, such as a logical one, may represent adefault or initial state, while a second value, such as a logical zero,may represent a non-default state. In addition, the terms reset and set,in one embodiment, refer to a default and an updated value or state,respectively. For example, a default value potentially includes a highlogical value, i.e. reset, while an updated value potentially includes alow logical value, i.e. set. Note that any combination of values may beutilized to represent any number of states.

The embodiments of methods, hardware, software, firmware or code setforth above may be implemented via instructions or code stored on amachine-accessible, machine readable, computer accessible, or computerreadable medium which are executable by a processing element. Anon-transitory machine-accessible/readable medium includes any mechanismthat provides (i.e., stores and/or transmits) information in a formreadable by a machine, such as a computer or electronic system. Forexample, a non-transitory machine-accessible medium includesrandom-access memory (RAM), such as static RAM (SRAM) or dynamic RAM(DRAM); ROM; magnetic or optical storage medium; flash memory devices;electrical storage devices; optical storage devices; acoustical storagedevices; other form of storage devices for holding information receivedfrom transitory (propagated) signals (e.g., carrier waves, infraredsignals, digital signals); etc., which are to be distinguished from thenon-transitory mediums that may receive information there from.

Instructions used to program logic to perform embodiments of thedisclosure may be stored within a memory in the system, such as DRAM,cache, flash memory, or other storage. Furthermore, the instructions canbe distributed via a network or by way of other computer readable media.Thus a machine-readable medium may include any mechanism for storing ortransmitting information in a form readable by a machine (e.g., acomputer), but is not limited to, floppy diskettes, optical disks,Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks,Read-Only Memory (ROMs), Random Access Memory (RAM), ErasableProgrammable Read-Only Memory (EPROM), Electrically ErasableProgrammable Read-Only Memory (EEPROM), magnetic or optical cards, flashmemory, or a tangible, machine-readable storage used in the transmissionof information over the Internet via electrical, optical, acoustical orother forms of propagated signals (e.g., carrier waves, infraredsignals, digital signals, etc.). Accordingly, the computer-readablemedium includes any type of tangible machine-readable medium suitablefor storing or transmitting electronic instructions or information in aform readable by a machine (e.g., a computer).

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present disclosure. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

In the foregoing specification, a detailed description has been givenwith reference to specific exemplary embodiments. It will, however, beevident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the disclosure asset forth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative sense rather than arestrictive sense. Furthermore, the foregoing use of embodiment andother exemplarily language does not necessarily refer to the sameembodiment or the same example, but may refer to different and distinctembodiments, as well as potentially the same embodiment.

1. (canceled)
 2. A processor comprising: a core to execute a virtualmachine monitor to support a virtual machine, wherein the virtualmachine is to execute guest software; and memory management hardware tomap a guest virtual address to a guest physical address of a page, tomap the guest physical address to a host physical address, and todetermine whether to allow access to the page based on a first bit and asecond bit in a page table entry for mapping the guest physical addressto the host physical address, wherein the first bit is to indicatewhether the page is associated with a user mode or a supervisor mode andthe second bit it to indicate whether the page is accessible forexecution in a guest user mode, and to store the page table entry in atranslation lookaside buffer if the access is allowed.